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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-08460 rev. *c revised june 19, 2017 MB39C022G/j/l/n buck dc/dc converter + low noise ldo description the mb39c022 is a 2 channels power supply ic. it consists of one channel buck dc/dc converter and one channel ldo regulator. the dc/dc converter has fast transient resp onse with current mode control topology. moreover, the integrated ldo provides an auxiliary output supply for noise sensitive circuit. features power supply voltage range : 2.5 v to 5.5 v for buck dc/dc included sw fet (ch1) : ou tput 0.8 v to 4.5 v, 600 ma max dc for ldo (ch2) : output 3.30 v (MB39C022G) 300 ma max dc : output 2.85 v (mb39c022j) 300 ma max dc : output 1.80 v (mb39c 022l) 300 ma max dc : output 1.20 v (mb3 9c022n) 300 ma max dc error amplifier threshold voltage : 0.3 v (2.5 %) (ch1) fast line transient response wi th current mode topology (ch1) pfm mode at light load current with vo1/vin1 80 % (io1 10 ma) (ch1) power-on-reset with 66 ms delay (ch1) built-in short circuit protect (ch2) built-in over current protect (ch1, ch2) built-in thermal protection function small size plastic son- 10 (3 mm 3 mm) package applications portable equipment pnd, gps pmp mobile tv, usb-dongle (cmmb, dvb-t, dmb-t) smart-phone mp3
document number: 002-08460 rev. *c page 2 of 29 MB39C022G/j/l/n contents description ............. ........................ ..................... ................... 1 features ..................... ..................... ..................... ................... 1 applications ........... ........................ ..................... ................... 1 1. pin assignment .............. ............................ ...................... 3 2. pin descriptions .............................. .................. ............... 4 3. i/o terminal equivalent ci rcuit diagram .. ...................... 5 4. block diagram ................ ............................ ...................... 6 5. function descriptions ....... ......................... ...................... 7 5.1 pfm/pwm logic control block (ch1) ...................... 7 5.2 level converter and iout comparator circuit (ch1) ... 7 5.3 error amp. circuit (ch1 ) ...................... ...................... 7 5.4 ldo block (ch2) ........ ......................... ...................... 7 5.5 por block .... ..................... ..................... ................... 7 5.6 reference voltage block (vref) ........ ...................... 7 5.7 under voltage lockout protection circuit block (uvlo) ............... ............................... .......................... 8 5.8 over temperature protec tion block (otp) ............... 8 5.9 control block (ctl) .... ......................... ...................... 8 6. absolute maximum ratings ...................... ...................... 9 7. recommended operating c onditions .......................... 10 8. electrical characteristics ........................... .................... 11 9. test circuit for me asuring typical operating characteristics .................. ......................... .................... 13 10. application notes ......... ............................ .................... 14 10.1 selection of components ........ ............................... 14 10.2 dc/dc output voltage setting ........... .................... 15 10.3 power on reset (por ) ..................... .................... 15 10.4 power dissipation and he at considerations ........... 16 10.5 board layout, design example ........... .................... 17 11. example of standard operation characteristics ...... 18 11.1 dc/dc conversion effi ciency ............................... 18 11.2 dc/dc load regulation .................... .................... 18 11.3 dc/dc line regulation ..................... .................... 19 11.4 dc/dc switching wave form ................ ................. 19 11.5 ldo load regulation ........................ .................... 20 11.6 ldo line regulation ......................... .................... 20 11.7 ldo power supply reje ction ratio ...................... 21 11.8 dc/dc load transient waveforms ....................... 21 11.9 dc/dc power mos fet on resistance .............. 22 12. application circuits exam ples ................ .................... 24 13. usage precautions .......... ......................... .................... 26 14. ordering information ....... ......................... .................... 26 15. rohs compliance informat ion ................ .................... 26 16. package dimension ......... ......................... .................... 27 document history .. ........................ ..................... ................. 28 sales, solutions, and legal in formation ........................... 29
document number: 002-08460 rev. *c page 3 of 29 MB39C022G/j/l/n 1. pin assignment (top view) (wnk010) en2 vin2 vout2 gnd2 por gnd1 lx vin1 fb en1 24 35 1 76 8 9 10
document number: 002-08460 rev. *c page 4 of 29 MB39C022G/j/l/n 2. pin descriptions block pin no. pin name i/o descriptions ch1 (buck dc/dc) 6 fb i ch1 error amplifier input pin 9 lx o ch1 inductor connection pin ch2 (ldo) 3 vout2 o ch2 ldo output pin control 7 en1 i ch1 control pin (l : shutdown / h : operation) 1 en2 i ch2 control pin (l : shutdown / h : operation) power 8 vin1 ? ch1 power supply pin 2 vin2 ? ch2 power supply pin 10 gnd1 ? ch1 ground pin 5 gnd2 ? ch2 ground pin power-on reset 4 por o ch1 power on re set output pin (n mos open drain)
document number: 002-08460 rev. *c page 5 of 29 MB39C022G/j/l/n 3. i/o terminal equivalent circuit diagram gnd1 vin1 lx gnd2 po r g nd2 vin1 en ? g nd2 vin1 fb gnd2 vin2 vout2 ? ? ? ? ? ? * : esd protection device
document number: 002-08460 rev. *c page 6 of 29 MB39C022G/j/l/n 4. block diagram current limit pfm pwm logic control icomp fb por 6 4 por drv osc vref ocp/scp error amp. error amp. otp uvlo 8 9 level conv. 10 7 1 2 3 5 enb1 (h: ch1 on) enb2 (h: ch2 on) en1 en2 vin or vo1 vin1 lx gnd1 vin2 vout2 gnd2 <> <> io2 (300 ma max) vo2 io1 (600 ma max) vo1 (0.8 v to 4.5 v) vin (2.5 v to 5.5 v) <<10 pin>> por 3.3 v: MB39C022G 2.85 v: mb39c022j 1.8 v: mb39c022l 1.2 v: mb39c022n
document number: 002-08460 rev. *c page 7 of 29 MB39C022G/j/l/n 5. function descriptions 5.1 pfm/pwm logic control block (ch1) the built-in p-ch and n-ch mos fets are co ntrolled for synchronization rectification according to th e frequency (2.0 mhz) oscil lated from the built-in oscillator (square wave oscillation ci rcuit). under light load, it operates intermittently. this circuit protects the through current caused by synchronous rectification and th e reverse current in discontinuous conducti on mode. since the pwm control circuit of this ic is in the control met hod in current mode, the current peak value is monitored and cont rolled as required. 5.2 level converter and iout comparator circuit (ch1) the level converter circuit detects the curren t (ilx) which flows to the external inductor from the built-in p-ch mos fet. by c omparing videt obtained through i-v c onversion of peak current i pk of ilx with the error amp. output, the iout comparator turns off the built-in p-ch mos fet via the pwm logic control circuit. 5.3 error amp. circuit (ch1) the error amplifier (error amp.) de tects the output voltage from the dc/dc conver ter and output to the current comparators (ico mp). the output voltage setting resistor ex ternally connected to fb allows an arbitrary ou tput voltage to be set. 5.4 ldo block (ch2) the integrated low noise lo w dropout regulator (ldo) is avail able up to 300 ma current capabili ty and 700 ma over current prote ction (ocp) 350 ma short circuit protection (scp ). the ldo output vout2 requires a 4.7 f capacitor for MB39C022G and mb39c022n and a 1.0 f capacitor for mb39c022j and mb39c0 22l for stability. MB39C022G, mb39c022j, mb39c022l and mb39c022n have fixed 3.3 v, 2.85 v, 1.8 v and 1.2 v output voltages respectively, eliminating the need for an external resistor divider. 5.5 por block the por circuit monitors the vo1 through the fb pin voltage. when the fb pin voltage reaches 97% of v fbth , por pin becomes high level after the hold time of 66 ms. th e por pin is an open-drain output and pulled up to vin or vo1 with an external resis tor. timing chart : (por pin pulled up to vin with resistor) 5.6 reference voltage block (vref) a high accuracy reference voltage is generat ed with bgr (bandgap reference) circuit. vin en1 fb por t hold t hold v th 97% v uvlo v uvlo : uvlo threshold voltage (vt lh = 2.050 v) v th : fb pin threshold voltage (v th = 0.3 v)
document number: 002-08460 rev. *c page 8 of 29 MB39C022G/j/l/n 5.7 under voltage lockout protection circuit block (uvlo) the circuit protects against ic malfuncti on and system destruction/deterioration in a transitional state or a momentary drop of when the internal reference voltage starts. it detec ts a voltage drop at the vin1 pin and stop s ic operation. when voltages at the v in1 pin exceed the threshold voltage of th e under voltage lockout protection circuit, the system is restored. 5.8 over temperature protection block (otp) the circuit protects an ic from heat-destr uction. if the junction temperature reache s 135c, the circuit turns off the ch1 and ch2 operation, when the junction temperature comes down to + 110c, the ch1 and ch2 are re turned to the normal operation. 5.9 control block (ctl) control function table en1 en2 ch1 and por ch2 vref, uvlo, otp l l off off off hl on off on lh off on on h h on on on
document number: 002-08460 rev. *c page 9 of 29 MB39C022G/j/l/n 6. absolute maximum ratings *1 : when mounted on four layer ep oxy board of 11.7 cm 8.4 cm *2 : at connect the exposure pad and wi th thermal via (thermal via 4 pcs). *3 : at connect the exposure pad and not thermal via. *4 : power dissipation value between + 25c and + 85c is obtained by connecting th ese two points with a straight line notes: ? the use of negative voltages below ? 0.3 v to the gnd pin may create parasitic transistors on lsi lines, which can cause abnormal operation. ? if lx terminal is short-circuited to vin1 or vin2 or gnd line, there is a possibili ty to destroy it. such usage is prohibit warning: semiconductor devices can be permanently damaged by applic ation of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol condition rating unit min max power supply voltage vin1 vin1 pin ? 0.3 + 6.0 v vin2 vin2 pin ? 0.3 vin1 + 0.3 v input voltage vfb fb pin ? 0.3 vin1 + 0.3 v ven1 en1 pin ? 0.3 + 6.0 v ven2 en2 pin ? 0.3 + 6.0 v por pull-up voltage vpor por pin ? 0.3 + 6.0 v lx voltage vlx lx pin ? 0.3 vin1 + 0.3 v lx peak current ilx lx pin ac ? 1.6 a vout2 peak current io2 vout2 pin ac ? 0.8 a power dissipation pd ta + 25c ? 2632* 1, * 2 mw ? 980* 1, * 3 ta = + 85c ? 1053* 1, * 2, * 4 ? 392* 1, * 3, * 4 storage temperature t stg ? ? 55 + 125 c
document number: 002-08460 rev. *c page 10 of 29 MB39C022G/j/l/n 7. recommended operating conditions *1 : the minimum vin1 has to meet two conditions : vin1 (vin1 min) and vin1 vo1 + 0.5 v *2 : the minimum vin2 has to meet two conditions : vin2 (vin2 min) and vin2 vo2 + vdrop (vo2 and vdrop values are specified in ? electrical characteristics?) *3 : vin1 vin2 *4 : vin1 startup rise time 1 ms is recommended *5 : pfm mode at light load current with vo1/vin1 80% (io1 10 ma) warning: the recommended operating conditions are required in order to ensure th e normal operation of the semiconductor device. all of the device's el ectrical characteristi cs are warranted when the device is operated within these ranges. always use semiconductor devi ces within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respec t to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the list ed conditions are advised to contact their representatives beforehand. parameter symbol condition value unit min typ max power supply voltage vin1 vin1 pin* 1, * 3, * 4, * 5 2.5 3.7 5.5 v vin2 vin2 pin* 2, * 3 input voltage vfb fb pin ? 0.30 ? v ven1 en1 pin 0 ? 5.5 v ven2 en2 pin 0 ? 5.5 v output voltage vo1 ch1 : buck dc/dc* 1, * 5 0.8 ? 4.5 v output current ilx lx pin dc ? ? 0.6 a ivout2 vout2 pin dc ? ? 0.3 a operating ambient temperature ta ? ? 40 + 25 + 85 c
document number: 002-08460 rev. *c page 11 of 29 MB39C022G/j/l/n 8. electrical characteristics (ta = + 25c, vin1 = vin2 = 3.7 v) parameter symbol pin no. condition value unit min typ max ch1 [ buck dc/dc ] threshold voltage vth 6 fb pin ? 2.5% 0.3 + 2.5% v input bias current ifb 6 fb = 0 v ? 1000 + 100 na sw pmos-tr on resistor rpon 8,9 ilx = ? 100 ma ? 0.35 ? ? sw nmos-tr on resistor rnon 9,10 ilx = 100 ma ? 0.25 ? ? line regulation vline1 ? vin1 = 2.5 v to 5.5 v* 1 ? 10 ? mv load regulation vload1 ? io1 = 100 ma to 600 ma ? 10 ? mv over current protect ilim1 9 vout1 0.9 0.9 1.2 1.5 a ch2 [ ldo ] output voltage vo2 3 io2 = 0 ma to ? 300 ma MB39C022G ? 2.5% 3.30 + 2.5% v io2 = 0 ma to ? 300 ma mb39c022j ? 2.5% 2.85 + 2.5% v io2 = 0 ma to ? 300 ma mb39c022l ? 2.5% 1.80 + 2.5% v io2 = 0 ma to ? 300 ma mb39c022n ? 2.5% 1.20 + 2.5% v line regulation vline2 3 vin2 = 2.5 v to 5.5 v* 2 ? ? 10 mv load regulation vload2 3 io2 = 0 ma to ? 300 ma ? ? 25 mv drop out voltage vdrop 3 io2 = ? 300 ma, vin2 = vo2 : MB39C022G, mb39c022j ? 200 ? mv power supply rejection ratio psrr 3 MB39C022G* 3 f = 1 khz ? 70* 4 ? db f = 10 khz ? 70* 4 ? db mb39c022j* 3 f = 1 khz ? 65* 4 ? db f = 10 khz ? 65* 4 ? db mb39c022l* 3 f = 1 khz ? 60* 4 ? db f = 10 khz ? 60* 4 ? db mb39c022n* 3 f = 1 khz ? 55* 4 ? db f = 10 khz ? 55* 4 ? db output noise voltage vnoise 3 f = 10 hz to 100 khz, en1 = 0 v ? 55* 4 ? vrms over current protect ilim2 3 vo2 0.9 500 700 980 ma short circuit protect iscp2 3 vo2 = 0 v 150 350 700 ma
document number: 002-08460 rev. *c page 12 of 29 MB39C022G/j/l/n (ta = + 25c, vin1 = vin2 = 3.7 v) *1 : the minimum vin1 has to meet two conditions : vin1 (vin1 min) and vin1 vo1 + 0.5 v *2 : the minimum vin2 has to meet two conditions : vin2 (vin2 min) and vin2 vo2 + vdrop (vo2 and vdrop values are specified in ? electrical characteristics?) *3 : vin2 = vo2 + 1 v, (mb39c022n: vin2 = 2.5 v), io2 = 100 ma *4 : this value is not be specified. this should be used as a reference to sup port designing the circuits. parameter symbol pin no. condition value unit min typ max power on reset [ por ] hold time thold 4 fosc = 2 mhz 52.8 66 79.2 ms output voltage vpor 4 por = 250 a ? ? 0.1 v output current ipor 4 por = 5.5 v ? ? 1 a under voltage lockout protection circuit block [ uvlo ] threshold voltage vthl 2, 8 vin1 1.95 2.10 2.25 v hysteresis width vh 2, 8 ? ? 0.20 ? v over temperature protection block [ otp ] stop temperature totph ? ? ? + 135 ? c hysteresis width totphys ? ? ? + 25 ? c oscillator block [ osc ] output frequency fosc 9 ? 1.6 2.0 2.4 mhz control block [ctl ] input voltage vih 1, 7 en1, en2 on 1.5 ? ? v vil 1, 7 en1, en2 off ? ? 0.4 v input current ien 1, 7 en1, en2 = 0 v ? 100 0 + 100 na general shut down power supply current icc1 8 en1, en2 = 0 v ? 0 1 a icc1 2 en1, en2 = 0 v ? 0 1 a standby power supply current (dc/dc) icc2 8 en1 = vin1, en2 = 0 v io1 = 0 ma, vfb = vin1 ? 30 60 a icc2 2 ? 0 1 standby power supply current (ldo) icc3 8 en1 = 0 v, en2 = vin1 io2 = 0 ma ? 10 18 a icc3 2 ? 60 120 power-on invalid current icc4 8 en1, en2 = vin1, vfb = 0.2 v ? 0.9 1.5 ma icc4 2 ? 60 120 a
document number: 002-08460 rev. *c page 13 of 29 MB39C022G/j/l/n 9. test circuit for measuring typical operating characteristics * : the output voltage of vo1 can be adju sted by the external resistor divider r5. component item specification remarks c1 ceramic capacitor 10 f c2 ceramic capacitor 4.7 f c3 ceramic capacitor 22 pf c4 ceramic capacitor 4.7 f c5 ceramic capacitor 1 f for mb39c022j, mb39c022l 4.7 f for MB39C022G, mb39c022n l1 inductor 2.2 h r3 resistor 1 m ? r5 resistor 600 k ? at vo1 = 1.2 v* r6 resistor 200 k ? v o1 = v ref (r5 + r6) = 0.3 v (600 k ? + 200 k ? ) = 1.2 v r6 200 k ? en2 vin2 vout2 por gnd2 fb en1 vin1 lx gnd1 vo1 vin por en2 en1 c4 c5 c2 c1 l1 r6 r3 c3 r5 vo2
document number: 002-08460 rev. *c page 14 of 29 MB39C022G/j/l/n 10. application notes 10.1 selection of components selection of an external inductor for dc/dc this ic is designed to operate well with a 2.2 h inductor. choosing larger values would lead to larger overshoot/undershoot during load transient. choosing a smaller value would lead to larger ripple voltage. the inductor should be rated for a saturati on current higher than the lx peak curr ent value during normal operating conditions, and should have a minimal dc resistance. (100 m ? or less is recommended to improve efficiency.) lx peak current value i pk is obtained by the following formula. l : external inductor value i out : load current (dc) v in : power supply voltage v out : output setting voltage d : on- duty to be switched ( = v out /v in ) fosc : switching frequency (2.0 mhz) ex) at v in = 3.7 v, v out = 1.2 v, i out = 0.6 a, l = 2.2 h, fosc = 2.0 mhz the maximum peak current value i pk ; i/o capacitor selection ? dc/dc's output capacitor's finite equival ent series resistance (esr) causes ripple vo ltages on output equal to the amount of current variation multiplied by the esr value. the output ca pacitor value also has a significant impact on the operating stabil ity of the device when used as a dc /dc converter. therefore, cypress generally recommends c2 = 4.7 f as dc/dc output capacitor, or a larger capaci tor value can be used if rippl e voltages are not suitable. ? for dc/dc, select a low esr for the vin1/v in2 input capacitor to suppress dissipation from ripple currents. in addition, to reduce startup overshoot for dc/d c and ldo, it is recommended th at larger ceramic capacitor be used for input capacitors c1 and c4. recommended va lues are c1 = 10 f, c4 = 4.7 f. ? types of capacitors ceramic capacitors are effective for re ducing the esr and afford smaller dc/dc c onverter circuit. however, power supply functions as a heat generator, therefore avoid using capacitor with the f-temperature rating ( ? 80% to + 20%). cypress recommends capacitors with the b-temperature rating ( 10 % to 20 % ). normal electrolytic capacitors are no t recommended due to their high esr. tantalum capacitor will reduce esr, however, it is dangerous to use be cause it turns into short mode when damaged. if you insist on using a tantalum capacitor, cypres s recommends the type wi th an internal fuse. i pk = i out + v in - v out d 1 = i out + (v in - v out ) v out l fosc 2 2 l fosc v in i pk = i out + (v in ? v out ) v out = 0.6 a + (3.7 v ? 1.2 v) 1.2 v = 0.69 a 2 l fosc v in 2 2.2 h 2 mhz 3.7 v
document number: 002-08460 rev. *c page 15 of 29 MB39C022G/j/l/n 10.2 dc/dc output voltage setting the output voltage v o1 of this ic is defined by the external resistive divider r5 & r6. note that c3 is a capacito r used for improving stability. use a 22 pf cap for c3 should be suitable in all cases. 10.3 power on reset (por) r3 and r4 are the pull-up resi stors for por (pin 4). a 1 m ? resistor is required to placed at either r3 or r4. when r3 has a 1 m ? resistor and r4 is open; the por will be connected vin. when r4 has a 1 m ? resistor and r3 is open; the por pin will be connected to vo1. by default, only r3 require a 1 m ? resistor while r4 is open. v o1 = v ref r5 + r6 = 0.3 v 600 k ? + 200 k ? = 1.2 v r6 200 k ? r6 r5 vo1 6 fb mb39c022 c3 - + vref (0.3 v)
document number: 002-08460 rev. *c page 16 of 29 MB39C022G/j/l/n 10.4 power dissipation and heat considerations the dc/dc is so efficient that no considerat ion is required in most cases. the ldo, on the other hand, woul d be the dominant he at generator due to its inherent effi ciency loss. thus, if the ic is used at a high power supply voltage, heavy lo ad, and low ldo output voltage, or high temperature, it requires further consideration. the internal loss (pc) is roughly obt ained from the following formula : p c = p c1 + p c2 = i o1 2 (rdc + d r onp + (1 - d) r onn ) + i o2 v drop p c1 : dc/dc continuity loss p c2 : ldo continuity loss rdc : external inductor series resistance ( < 100 m ? recommended) d : switching on-duty cycle ( = v out / v in ) r onp : internal p-ch sw fet on resistance r onn : internal n-ch sw fet on resistance i o1 : dc/dc load current i o2 : ldo load current v drop : ldo dropout voltage the loss expressed by the above fo rmula is continuity loss. the in ternal loss includes the swit ching loss and the control circu it loss as well but they are so sm all compared to the continuity loss they can be ignored. for p c1 , consider the scenario with high temper ature and heavy load (vin = 3.7 v, v o1 = 1.2 v, i o1 = 0.6 a, ta = + 70c). here, r onp 0.4 ? and r onn 0.3 ? according to the graph ?mos fet on resistance vs. oper ating ambient temperature?. p c1 = 156 mw. for p c2 , consider the scenario with low outp ut voltage (mb39c022n), high temper ature and heavy load (vin = 3.7 v, v o2 = 1.2 v, i o2 = 0.3 a, ta = + 70c). here, p c2 = 0.75 w. note that p c2 >> p c1 . according to the graph ?power dissipation vs. operating ambient temperature?, the ma ximum permissible power dissipation at an operating ambient te mperature ta of + 70c is 1.4 w. the internal loss is lowe r than the maximum permi ssible power dissipation.
document number: 002-08460 rev. *c page 17 of 29 MB39C022G/j/l/n 10.5 board layout, design example some basic design guidelines should be used when physically placing the mb39c022 on a printed circuit board (pcb). ? regarding to gnd pattern of pcb layout of mb39c022, it needs to separate like agnd (analo g ground) and pgnd (power ground). by separating grounds, it is possible to minimize the switch ing frequency noise on the ldo output. ? arrange the input capacitor c1 and c4 as close as possible between vi n1 & pgnd pins and vin2 & agnd pins. make a through hole near the pins of this capacitor if the board has planes for power and gnd. ? large ac currents flow between th is ic and the input capacitor (c1), output capacitor (c2), and external inductor (l1). group these components as close as possibl e to this ic to reduce the overall loop area occupied by this group. also try to mount thes e components on the same su rface and arrange wiring wi thout through hole wiring. use thick, short, and straight routes to wire the net (the layout by planes is recommended.). ? the c1 and c2 capacitor returns are conn ected closely together at the pgnd plane. ? the ldo input capacitor (c4) and ldo output capacitor (c5) are returned to the agnd plane. ? the analog ground plane and power gr ound plane are connected at one point. ? all other signals (en1, en2, fb) should be referenced to agnd and ha ve the agnd plane underneath them. ? the feedback wiring to the v o1 and the v o1 pin should be wired closest to the output capacitor (c2). the resistive divider and fb pin is extremely sensitive and should thus be kept wired away from the lx pin of this ic as far as possible. ? try to make a gnd plane on the surface to which this ic will be mo unted. for efficient heat dissi pation when using the son-10 package, cypress recommends providing a ther mal via in the footprin t of the thermal pad. layout example of ic components agnd a g n d agnd pgnd pgnd vin2 v i n 2 vin2 vin1 v i n 1 vin1 c4 c 4 c4 c2 c 2 c2 c1 c 1 c1 r6 r 6 r6 r5 r 5 r5 l1 c5 c5 c 5 c5 v o 2 vo2 vo1 pgnd plane agnd plane
document number: 002-08460 rev. *c page 18 of 29 MB39C022G/j/l/n 11. example of standard operation characteristics (shown below is an example of characteri stics for connection according to ? test circuit for measuring typical operating characteristics?.) 11.1 dc/dc conversion efficiency 11.2 dc/dc load regulation 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 load current io1 (a) conversion efficiency (%) vin = 3.7 v vin = 4.3 v vin = 5.5 v ch1 test condition : en1 = vin; en2 = 0 v vo1 = 1.2 v; c1 = 10 f; c2 = 4.7 f 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 0 0.2 0.4 0.6 load current io1 (a) output voltage vo1 (v) vin = 3.7 v vin = 4.3 v vin = 5.5 v ch1 test condition : en1 = vin; en2 = 0 v vo1 = 1.2 v; c1 = 10 f; c2 = 4.7 f
document number: 002-08460 rev. *c page 19 of 29 MB39C022G/j/l/n 11.3 dc/dc line regulation 11.4 dc/dc switching waveform 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 3.2 3.7 4.2 4.7 5.2 input voltage vin (v) output voltage vo1 (v) io1 = 0 ma io1 = 300 ma io1 = 600 ma ch1 test condition : en1 = vin; en2 = 0 v vo1 = 1.2 v; c1 = 10 f; c2 = 4.7 f 500 ns /div vlx 5 v/div ilx 100 ma/div vo1 20 mv/div vo2 20 mv/div ch1 test condition : en1 = en2 = vin = 3.7 v; vo1 = 1.8 v; io1 = 250 ma; c1 = 10 f; c2 = 4.7 f vo2 = 3.3 v; io2 = 150 ma; c4 = c5 = 4.7 f
document number: 002-08460 rev. *c page 20 of 29 MB39C022G/j/l/n 11.5 ldo load regulation 11.6 ldo line regulation 0 3.2 3.22 3.24 3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 0.05 0.1 0.15 0.2 0.25 0.3 vin = 3.7 v vin = 4.3 v vin = 5.5 v MB39C022G ch2 test condition : en2 = vin; en1 = 0 v vo2 = 3.3 v; c4 = c5 = 4.7 f load current io2 (a) output voltage vo2 (v) 3.4 3.38 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 3.2 3.6 4.1 4.6 5.1 io2 = 0 ma io2 = 120 ma io2 = 300 ma MB39C022G ch2 test condition : en2 = vin; en1 = 0 v vo2 = 3.3 v; c4 = c5 = 4.7 f input voltage vin (v) output voltage vo2 (v)
document number: 002-08460 rev. *c page 21 of 29 MB39C022G/j/l/n 11.7 ldo power supply rejection ratio 11.8 dc/dc load transient waveforms frequency (hz) psrr (db) 10 vin = 3.7 v vin = 4.3 v 100 1000 10000 100000 1000000 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 MB39C022G ch2 test condition : en2 = vin = 3.7 v; en1 = 0 v vo2 = 3.3 v; io2 = 100 ma; c1 = c4 = 0 f io1 = 10 ma to 400 ma io2 = 150 ma 100 s/div t io1 500 ma/div vo2 20 mv/div vo1 100 mv/div test condition : vin = en1 = en2 = 3.7 v; vo1 = 1.2 v; c1 = 10 f; c2 = 4.7 f; vo2 = 3.3 v; c4 = c5 = 4.7 f ch1 load transient waveforms
document number: 002-08460 rev. *c page 22 of 29 MB39C022G/j/l/n 11.9 dc/dc power mos fet on resistance 0.6 p-ch n-ch 0.5 0.4 0.3 0.2 0.1 0.0 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.0 3.0 4.0 5.0 6.0 -50 0 50 100 -50 0 50 100 v in = 3.7 v v in = 5.5 v v in = 3.7 v v in = 5.5 v input voltage v in (v) operating ambient temperature ta (c) n-ch mos fet on resistance vs. operating ambient temperature operating ambient temperature ta (c) mos fet on resistance vs. input voltage p-ch mos fet on resistance vs. operating ambient temperature p-ch mos fet on resistance r on ( ? ) mos fet on resistance r on ( ? ) n-ch mos fet on resistance r on ( ? )
document number: 002-08460 rev. *c page 23 of 29 MB39C022G/j/l/n 3000 2500 2000 1500 1000 500 0 -40 -20 0 20 40 60 80 100 2630 permissible power dissipation vs. operating ambient temperature operating ambient temperature ta (c) power dissipation p d (mw)
document number: 002-08460 rev. *c page 24 of 29 MB39C022G/j/l/n 12. application circuits examples example 1 (vin1 = vin2) vin1 and vin2 are connected togeth er and por is pulled up to vin example 2 (vin2 = vo1) ? vin2 is connected to vo1 and por is pulled up to vin ? it is possible to maximize ldo efficiency by connecting dc/dc ou tput to ldo supply. ? maximum dc/dc output current ( = io1 ) is limited by vin2 input current ( io2) en2 vin2 vout2 por gnd2 fb en1 vin1 lx gnd1 por en2 en1 c4 c5 c2 c1 l1 r5 r3 c3 r6 vo1 io1 600 ma vo2 io2 300 ma (mb39c022) vin en2 vin2 vout2 por gnd2 fb en1 vin1 lx gnd1 por en2 en1 c4 c5 c2 c1 l1 r5 r3 c3 r6 vo1 io1 600 ma - io 2 vo2 i o2 300 ma (mb39c022) vin
document number: 002-08460 rev. *c page 25 of 29 MB39C022G/j/l/n example 3 (por and rc delay channel control) ? en1 is controlled by rc delay and en2 is controlled by por output. ? it is possible to control each channel without signal from mcu en2 vin2 vout2 por gnd2 fb en1 vin1 lx gnd1 por c4 c5 c2 c1 l1 r6 r3 c3 vo1 io1 600 ma vo2 io2 300 ma (mb39c022) r5 100 k 1 f vin vin vo1 (1.2 v) vo2 (1.8 v) t a t b v uvlo v th (por) t c t d timing chart start up control t a : rc delay time (28 ms at vin = 3.7 v, r = 100 k ? , c = 1 f) t b : por hold time (66 ms fixed) power down control t c , t d : depend on internal discharge path and output loading
document number: 002-08460 rev. *c page 26 of 29 MB39C022G/j/l/n 13. usage precautions 1. never use setting exceeding maximum rated conditions . semiconductor devices can be permanently da maged by application of st ress (voltage, current, temper ature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 2. use the devices within recommended conditions it is recommended that devices be oper ated within recommended conditions. exceeding the recommended oper ating condition may adversely affect devices reliability. nominal electrical characteristics are warra nted within the range of recommended opera ting conditions otherwise specified on ea ch parameter in the section of electrical characteristics. 3. design the ground line on printed circuit boar ds with consideration of common impedance. 4. take appropriate measures against static electricity. the lx pin has less bu ilt-in esd protection than other pins. lx pin : 150 v (mm), 1500 v (hbm), oth er pins : 200 v (mm), 2000 v (hbm) containers for semiconductor materials should have anti-static protection or be made of cond uctive material. after mounting, printed circuit boards should be stor ed and shipped in conducti ve bags or containers. work platforms, tools, and instrume nts should be properly grounded. working personnel should be gro unded with resistance of 250 k ? to 1 m ? between body and ground. 5. do not apply negative voltages the use of negative voltages below ? 0.3 v may activate parasitic tr ansistors on the device, which can cause abnormal operation. 14. ordering information 15. rohs compliance information the lsi products of cypress with ?e1? are compliant with rohs directive, and ha s observed the standard of lead, cadmium, mercur y, chromium, polybrominated biphenyls (pbb), and polybrominated di phenylethers (pbde). a product whose part number has trailing characters ?e1? is rohs compliant. part number package remarks MB39C022Gpn 10-pin plastic son (wnk010) ? mb39c022jpn mb39c022lpn mb39c022npn
document number: 002-08460 rev. *c page 27 of 29 MB39C022G/j/l/n 16. package dimension millimeter nom. min. b e 2.40 bsc 3.00 bsc d a 1 a 3.00 bsc 0.00 symbol max. 0.75 0.05 0.50 bsc l 0.22 0.25 0.28 e d 2 2 1.70 bsc e c 0.30 ref 0.40 0.30 0.50 2. dimensioning and tolerancinc conforms to asme y14.5-1994. 3. n is the total number of terminals. 4. dimension "b" applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip.if the terminal has the optional radius on the other end of the terminal. the dimension "b"should not be measured in that radius area. 5. nd refer to the number of terminals on d or e side. 6. max. package warpage is 0.05mm. 1. all dimensions are in millimeters. 7. maximum allowable burrs is 0.076mm in all directions. 8. pin #1 id on top will be located within indicated zone. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. note 10. jedec specification no. ref : n/a side view bottom view top view d a e b 0.10 c 2x 0.10 c 2x 0.10 c a a1 0.05 c c seating plane d2 e2 0.10 c a b 0.10 c a b 10 e b 0.10 c a b 0.05 c (nd-1) e index mark 8 4 5 9 l 9 6 1 5 package code: wnk010 002-15676 rev. **
document number: 002-08460 rev. *c page 28 of 29 MB39C022G/j/l/n document history document title: MB39C022G/j/l/n bu ck dc/dc converter + low noise ldo document number: 002-08460 revision ecn orig. of change submission date description of change ** ? taoa 04/13/2009 initial release *a 5150068 taoa 02/24/2016 migrated spansion data sheet from ds04-27271-2e to cypress format *b 5640458 hixt 02/23/2017 updated pin assignment : change the package name from lcc-10p-m04 to wnk010 updated ordering information : change the package name from lcc-10p-m04 to wnk010 updated package dimension : updated to cypress format *c 5777611 masg 06/19/2017 adapted cypress new logo.
document number: 002-08460 rev. *c revised june 19, 2017 page 29 of 29 ? cypress semiconductor corporation, 2009-2017. this document is the property of cypre ss semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmwa re included or referenced in this document (?software?), is owne d by cypress under the intellec tual property laws and treaties of th e united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patent s, copyrights, trad emarks, or other intellectual property right s. if the software is not accomp anied by a license agreement and yo u do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (witho ut the right to sublicense) (1) under its copyright rights in the software (a) for softwa re provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in bi nary code form externally to end users (either directly or indirectly through rese llers and distributors), solely for use on cy press hardware produc t units, and (2) u nder those claims of cypress?s patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import t he software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translati on, or compilation of the software is prohibited. to the extent permitted by applicab le law, cypress makes no warrant y of any kind, express or implie d, with regard to this docum ent or any software or accompanying hardware, includ ing, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypr ess reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the applicati on or use of any product or circuit described in this document. any informati on provided in this document, incl uding any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this docum ent to properly design, prog ram, and test the functional ity and safety of any appli cation made of this information and any resulting product. cypress products are not designed, inte nded, or authorized for use as critical components in systems designe d or intended for the operation of w eapons, weapons systems, nuclear instal lations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management , or other uses wher e the failure of the device or system could cause per sonal injury, death, or property damage (?uninte nded uses?). a critical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypre ss from any claim, damage, or other liability arisi ng from or related to all unin tended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for pe rsonal injury or death, arising from or related to any un intended uses of cypress products. cypress, the cypress logo, spansion, the spansion l ogo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or regist ered trademarks of cypress in the united states and other countries. for a more complete li st of cypress trademar ks, visit cypress.com. other names and bra nds may be claimed as property of their respective owners.. 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